For professional Verilog designers, in most cases currently open source synthesis tool and place&route tool are no alternative to the propriety solutions available.

But Yosys can be used to test for bugs in your design caused by bugs in the commercial toolchain.

Generate with your commerical tool from your Verilog design a RTL file, run your Verilog design through Yosys, and test the two for equalness also with Yosys. If the test is not positive, than there is something wrong.

This way we found about 18 bugs in commercial tools which generated faulty bitstreams.