This is for ...

  • Verilog programmers
  • HDL tool designers

icoTC Verilog-to-bitstream FPGA toolchain

the icoTC is currenlty available for Windows and Linux

Link to Windows version

High level Synthesis tools for FPGAs

Migen Python FPGA programming

MISOC System (might fit on 8kLut Lattice)

MyHDL (Python HDL)

Shang C-to-Verilog project

OLCAcc (openCL to Verilog)

Verilog-to-RTL synthesis and formal verification

Verilog RTL Synthesis:  Yosys

Place and Route for FPGAs
Arachne-pnr (Linux)

FPGA device programming

iceprog and icoprog (Linux)

Lattice chip documentation and tools

Project Icestorm (Linux)

By using Yosys as synthesis tool, you keep your Verilog project platform independent.

Arachne is currently not able to generate bitstreams for Xilinx or Altera devices. But you can use Yosys to do the synthesis and use the vendor PnR tools to generate valid bitstreams.